The Beloved NAND
April 13th, 2022This week’s topic will be discussing NAND hardware. This relates to the Capstone building of a minimalistic OS, as within the level of hardware, you will find these lurking in many board areas. Maybe lurking is an odd word to use, the NAND gates have no intension of attack, much like their inputs, they are actually quite the opposite. Early in the program here at OSU, I remember there was a statement read somewhere about how a computer has the potential to be fully utilized with pure NAND gate logic. Thinking at the time oh, that is cool, okay thanks for the fun fact. Now, many courses later and independent exploring, this seems like a fascinating statement. To the interwebs! Okay, I’m back. Found a blog from a person who actually did just that, created a computer fully based on NAND chips, below you will find it in operation and here is a link to this person’s blog.
Here is a photo with some of the boards fully of only NAND chips, please visit this person’s blog listed above for more information and photos, including this one.
Sources for Content
NAND Gate Basics
The NAND chips you viewed in the photograph above are packaged die chips, they have a protective covering over a tiny chip, this chip has connection wiring to each of the pins. It shall also be noted, a single chip can and probably has multiple gates within it. The logic for the gates also does not have to be limited to only two inputs, as most internet representations will try to persuade you. In fact, you could have say eight inputs and one output or have one input split into a two-input place with a single output or other combos. Quick note, the last option listed is called an inverter or a NOT gate. With the possibilities of a NAND gate, it is considered to be functionally complete or a universal gate, just like a NOR gate. This bold statements means NAND gates alone have the ability to create any other logic function, hence the NANDputer possibility — and creation.
CMOS vs. TTL NAND Gates
Let us get the acronyms out of the way. CMOS stands for Complementary Metal Oxide Semiconductor and TTL stands for Transistor Transistor Logic. One more used later is MOSFET which stands for Metal Oxide Semiconductor Field Effect Transistor. “Metal Oxide Semiconductor” means the gate electrode is placed on an oxide insulator and this oxide insulator is on top of a semiconductor material. It is a fancy label for the stacking of materials. In the 1970s metal was actually used as the gate, however it has moved towards a non-metal medium — however we still use this term. These are very wordy, the rest of the blog will be using the acronyms. Most comparative reasoning will boil down to cost, however this will not be the focus of the comparison listed about these NAND gates. Below you will also see the inner-workings schematics of both types of NAND gates.
CMOS
CMOS actually has a combination of types, complementing each other, the NMOS and PMOS MOSFETs. The Bell Laboratory colleagues, Dawon Kahng and Mohamed Atalla, were responsible for the invention of the MOSFET. MOSFETS will have at least three terminals: source (could have multiple), gate, and drain. The movement of current between the drain and source is controlled by the voltage at the gate. For NMOS, the source/drain terminals are made of n-type semiconductors, while PMOS has the source/drain terminals made of p-type semiconductors/substrates.
But what are n-type and p-type semiconductors/substrates?
This labeling system all has to do with the impurities added to the pure silicon/germanium structure. P-type will have an additive with three-valence electrons, while n-type will have five-valence electrons. The silicon or germanium or other material lattice will have four-valence electrons. Therefore if the p-type or n-type additives are applied will either have create a “hole” where the electrons can jump about, filling each of the open places as seen in p-type, while n-type will have an extra electron randomly bouncing with no where to call home, it is far out from the nucleus of the additive, therefore its ties are not too great and the exploration can happen. Quick note on the additives, you could be surprised! P-type will have additives of elements with three-valence electrons, such as: aluminum, gallium, indium, and thallium. N-type will have additives of elements with five-valence electrons, such as: phosphorous, arsenic, antimony, and bismuth.
Now… back to the CMOS topic.
The CMOS process was created by a team of EEs at Fairchild Semiconductor Corporation, “Tom” Sah and Frank Wanlass. This process, the Complementary MOS establishes a clear path to output as the source of power (1) or ground (0). The power source paths mush be in complement to all the paths to ground. Meaning, the PMOS (p-type) transistors in parallel have corresponding NMOS (n-type) transistors in series, while the PMOS transistors in series have a corresponding NMOS transistor in parallel.
Here are some comments about the generalities of using a CMOS. CMOS uses little power for its NAND IC, making them the more preferred in practice and within products. The amount of time it takes for a signal to be received within a CMOS NAND IC is between 20-50nS. CMOS will require voltage levels 2/3 given power. CMOS is more sensitive to electromagnetic disruptions. More noise reduction can be found within CMOS. You can fit more logic within a given space using CMOS.
TTL
The original name for TTL was actually TCTL or Transistor Coupled Transistor Logic. I know, the statement above mentioned acronym would all be defined there, well, here is one more, I may add another later in the blog too. In 1961, EE James Buie of Thompson-Ramo-Woolridge Inc., invented the first TTL. A TTL NAND gate will have a bipolar (2 options) transistor with emitters as inputs, whose output will be buffered by an amplifier. Another acronym to have, BJT, stands for bipolar junction transistor. This is the grand name this logic has utilized too. Today, Texas Instruments has continued to have the standard for TTL IC chips manufacturing for usage, especially their 7400 NAND gate series.
Here are some comments about the generalities of using a TTL. The amount of time it takes for a signal to be received within a TTL NAND IC is 10nS. TTL will require voltage levels between 4.75 to 5.25 V. TTL is less sensitive to electromagnetic disruptions. Less noise reduction can be found within TTL. You can fit less logic within a given space using TTL. Some efforts have been made with creating chips which use less power than the original TTL design.
Visual Comparison
Interestingly, the CMOS will be the ultimate choice, however TTL will still be used as “glue logic” or parts of the circuitry for integration between integrated circuits (ICs). Another interesting fact to note, when the shift became apparent to move towards CMOS ICs, the manufacturers would create a chip with pins identical to layout of the TTL, for “easy” upgrades.
This diagram above shows the inner-workings of the CMOS and TTL. You can visually see the p-type and n-type MOS, which have the three: source, gate, and drain within the CMOS diagram. You can also see the complementary structure it holds between the p-type and n-type MOSFETs. The TTL shows the bubble label as the transistors. T1 in the diagram is the bi-polar possible entries or inputs, you can see the two options. The other transistors (T2, T3, T4) are used as an amplifier. Hopefully seeing the two visuals together will aide with solidifying the subjects spoke on within this post.
Thank you for reading.
