Our group has been developing an NES emulator, and we recently moved onto implementing the CPU. The NES CPU is a variation of the MOS Technology 6502, and contains 56 different op codes that can utilize 13 different addressing modes. These addressing modes inform the op codes as to which address against which to operate. I’m currently diving deep into the addressing modes, so wanted to detail my findings here.
The following details my notes around the 13 addressing modes, and how each operate:
Accumulator
These are instructions that operate against the currently value in the accumulator. They require two cycles to complete.
Absolute, Absolute X, Absolute Y
With this addressing mode, two additional bytes are read after the op code address that make up a word. This word defines a specific address against which to operate. These instructions can additionally be incremented by the value in the X or Y indexes. These instructions require 4 CPU cycles to complete. When indexing against the address, if incrementing the absolute address causes the address to cross pages (changes the value of the high byte) then an additional cycle is required.
Immediate
With this addressing mode 1 additional byte is read following the instruction. This byte represents a specific value against which to operate. This addressing mode requires 2 cycles.
Implied
The implied addressing mode basically means there is no addressing mode. These are instructions that operate against specific areas of memory. This are op codes like BRK and those that change processer flags directly. This addressing mode requires 2 cycles to complete.
Indirect
These instructions return a value located at a specific address. When this addressing mode is run, a word is read following the instruction which represents a memory location. This addressing mode then reads the value at that location and returns this value. Indirect requires 5 cycles.
Indirect X, Indirect Y
These are similar to the previous indirect. except a single byte is read following the instruction. This is then added to the zero page, and offset by the X or Y register. The word located at the calculated address is then returned. Indirect X increments without a carry operation, while Y is incremented and can carry. Indirect X uses 6 CPU cycles, while indirect Y uses 5. If indirect Y carries it uses 6 CPU cycles.
Relative
This addressing mode is used for branch operations. When used, a single byte following the instruction is read. This byte represents a signed integer that offsets from the current program counter. This instruction requires 2 cycles. If the offset causes the address to cross into a new page an additional cycle is required (for 3 total).
Zeropage, Zeropage X, Zeropage Y
This addressing mode targets values following a beginning of the memory (zeropage), and are very quick to run. When run a byte is read following the instruction representing an offset from the zero page. Zeropage X and Y additionally add the X or Y index (as applicable) to this offset. If the additional of the index causes the instruction to carry, the carry is dropped and the returned address instead just wraps back around to start at zero. They are mainly used to access frequently referenced variables. Zeropage requires 3 CPU cycles, while Zeropage X and Zeropage Y require 4.
Understanding and implementing these addressing modes are key to pushing forward on the opcodes themselves. Successfully implementing and testing various scenarios around addressing modes should make moving onto the opcodes themselves a much easier exercise.
This documentation is sourced primarily from 6502 Instruction Set (masswerk.at).
