I’m a fourth-year electrical and computer engineering student at Oregon State University with a focus in embedded firmware and digital logic design. For the past two summers, I have interned at Intel in Hillsboro, Oregon for a digital logic validation team. During my time at Intel, I have created many tools in Perl and Python, written SystemVerilog assertions, and restructured the test bench the team will use to validate the next generation IP. After graduation, I will be a full-time employee at Intel on an RTL validation team. My focus this year was learning more about SystemVerilog and VLSI to prepare for my job. If you would like to learn more about what I’ve been working on this past year, feel free to check out my portfolio.
